JOB DETAILS

Senior Static Timing Analysis (STA) Engineer

CompanyNXP Semiconductors
LocationTianjin
Work ModeOn Site
PostedApril 14, 2026
About The Company
We anticipate tomorrow’s needs—navigating a changing world by bringing together technology's brightest minds to build game-changing solutions that propel us forward. NXP Semiconductors N.V. (NASDAQ: NXPI) is the trusted partner for innovative solutions in the automotive, industrial & IoT, mobile, and communications infrastructure markets. NXP's "Brighter Together" approach combines leading-edge technology with pioneering people to develop system solutions that make the connected world better, safer, and more secure. The company has operations in more than 30 countries and posted revenue of $12.61 billion in 2024. Find out more at www.nxp.com. Career Development Opportunities : Bright Minds. Bright Futures. We believe that a key component to growing our business is to develop our people. To enable you to grow your career at NXP, we offer online and offline learning opportunities to help you develop some of your core and professional skills. Commitment At NXP. We recognize NXP is a powerful change agent as we continue to deliver innovative solutions that advance a more sustainable future. We remain steadfast in our commitment to sustainability and making measurable year-on-year progress. Also, we aim to create an inclusive work environment and we will not tolerate racism, discrimination or harassment of any kind. We have programs in place focused on diversity, inclusion and equality. Privacy Policy: https://www.nxp.com/company/about-nxp/privacy-policy-for-social-media-pages:PRIVACY-POLICY-SOCIAL-MEDIA
About the Role

Overview:

Expect experienced Senior STA Engineer to join our IC design team. This role will lead timing signoff activities for complex SoC projects, ensuring robust timing closure across multiple process, voltage, and temperature corners. Will collaborate closely with front‑end and back‑end design teams to drive high‑quality, high‑performance chip implementation.

Key Responsibilities:

  • Own full‑chip static timing analysis and signoff for advanced‑node SoC designs.
  • Develop and maintain STA constraints (SDC) and timing methodologies.
  • Perform block‑level and top‑level timing analysis, debug violations, and guide design teams toward closure.
  • Work with RTL, synthesis, and physical design teams to resolve setup/hold, clock skew, noise, and transition issues.
  • Optimize timing through constraint refinement, logic restructuring suggestions, ECO guidance, and physical optimization feedback.
  • Analyze and validate timing models, including Liberty (.lib), SPEF, and SDF.
  • Support timing‑related signoff flows, including OCV/AOCV/POCV, crosstalk analysis, and MCMM timing closure.
  • Provide technical leadership in methodology development, tool evaluation, and flow automation.
  • Collaborate with cross‑functional teams (DFT, power, architecture) to ensure consistent timing across all design modes and corners.
  • Mentor junior engineers on STA fundamentals, flow usage, and debugging techniques.

Qualifications:

  • Master’s degree in Electrical Engineering, Computer Engineering, or related field.
  • Strong English communication skills, including the ability to collaborate effectively with global teams and clearly articulate technical issues in English.
  • 5+ years of hands‑on STA experience in SoC development.
  • Strong proficiency with industry-standard STA tools (e.g., Synopsys PrimeTime, Cadence Tempus).
  • Solid understanding of timing concepts such as OCV/AOCV/POCV, clock tree synthesis, crosstalk, IP timing integration, and MCMM flows.
  • Familiarity with synthesis, place-and-route, and ECO flows.
  • Expertise with SDC constraints and timing debugging.
  • Strong scripting skills in Tcl, Perl, Python, or Shell.
  • Excellent problem‑solving abilities and communication skills.


More information about NXP in Greater China...

#LI-6650
Key Skills
Static Timing AnalysisSoC DesignSDCPrimeTimeTempusOCVAOCVPOCVCrosstalk AnalysisMCMMTclPerlPythonShellTiming ClosurePhysical Design
Categories
EngineeringTechnologySoftware
Benefits
Learning opportunitiesProfessional development programsDiversity and inclusion programs
Job Information
📋Core Responsibilities
The Senior STA Engineer will lead full-chip static timing analysis and signoff for advanced-node SoC designs. They will collaborate with cross-functional teams to ensure robust timing closure and mentor junior engineers on STA methodologies.
📋Job Type
full time
📊Experience Level
5-10
💼Company Size
22463
📊Visa Sponsorship
No
💼Language
English
🏢Working Hours
40 hours
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