ENG-HBM-LAYOUT

Design and development of analog, mixed-signal, custom digital block and full chip level integration support. Perform layout verification like LVS/DRC/Antenna, quality check and documentation. Responsible for on-time delivery of block-level layouts with acceptable quality. Will be leading planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment. Effectively communicating with Global engineering teams to assure the success of layout project. 5+ years in analog/custom layout design on advanced CMOS nodes (Planar, FinFET); BE/MTech in Electronics/VLSI or related field. Expertise in Cadence VLE/VXL and Mentor Calibre DRC/LVS for layout and verification. Hands-on experience with critical analog/mixed-signal blocks such as PLL, ADC/DAC, LDO, Bandgap, Charge Pump, Current Mirrors, and Amplifiers. Strong understanding of analog layout fundamentals (matching, EM, latch-up, IR-drop, parasitics) and layout impact on speed, power, and area. Ability to implement high-quality layouts under design constraints and ensure robust physical verification. Multiple Tape out support experience will be an added advantage. Experience in managing multiple layout projects, ensuring quality checks are taken care at all stages of layout development. Excellent command and problem-solving skills in physical verification of custom layout.