Principal Physical Design Engineer - MCU

NXP’s Industrial & IoT Edge solutions range from the smallest MCUs to very high-performance processors to provide real-time insights and efficient automation when performance matters most. NXP’s advanced portfolio of edge processing solutions lets developers explore their most innovative ideas with confidence, enabling applications across the autonomous home, industrial automation, and personal electronics.

NXP is building new teams in Catania to create high impact micro-controllers (MCU) as part of NXP’s intelligent AI at the Edge. This team will include a wide range of engineering talent from analog to SOC digital design. Full product development local will product world class products at a world class pace. 

This role will contribute to the physical design and implementation of complex, high-performance semiconductor integrated circuits, driving technical solutions in key areas such as static timing closure, floorplanning, place and route, and physical verification. The role also includes mentoring and developing junior engineers, while ensuring the timely delivery of cutting-edge products across NXP's diverse portfolio.

Your Responsibilities.

• Floorplanning, power grid design, place and route, low power implementation, clock tree synthesis, timing closure, power/signal integrity analysis, physical verification (DRC/LVS/Antenna).
• Drive the definition and implementation of physical design methodologies, flows, and best practices to optimize performance, power, and area.
• Perform comprehensive static timing analysis (STA) and ensure all timing constraints are met across various corners and modes.
• Conduct power integrity (IR drop) and signal integrity (Crosstalk) analysis and implement solutions to mitigate issues.
• Oversee and perform design rule checking (DRC), layout versus schematic (LVS), and other physical verification steps to ensure tape-out readiness.
• Collaborate closely with architecture, RTL design, DFT, and package teams to ensure seamless integration and successful product delivery.
• Mentor and provide technical guidance to junior and senior physical design engineers, fostering a culture of continuous learning and excellence.
• Evaluate and adopt new EDA tools and technologies to improve design efficiency and quality.

Your Profile.

• Bachelor's degree with 12+ years of professional experience or Master's degree with 10+ years of professional experience.
• Working knowledge on advance tech nodes 16ff and below is highly desirable.
• Extensive knowledge and experience in back-end implementation tasks such as (timing & power), synthesis, low power implementation, power analysis, equivalence checking and STA.
• Experience at top-level will be preferred.
• Expert-level proficiency with industry-standard EDA tools for physical design (e.g., Cadence Innovus, Synopsys Fusion Compiler/ICC2, Ansys RedHawk/PowerSI).
• Deep understanding of Static Timing Analysis (STA) concepts, sign-off criteria, and tools (e.g., Synopsys PrimeTime).
• Strong knowledge of power analysis and optimization techniques (e.g., UPF/CPF, clock gating, power intent).
• Proven experience with physical verification tools (e.g., Synopsys IC Validator, Cadence Pegasus/PVS, Mentor Calibre).
• Solid understanding of semiconductor device physics, process technology effects, and DFM/DFY considerations.
• Proficiency in scripting languages (e.g., Tcl, Python, Perl) for automation of design flows and analysis.
• Excellent problem-solving, analytical, and debugging skills.
• Strong communication and interpersonal skills, with the ability to effectively collaborate with cross-functional teams and mentor other engineers.
• Ability to work independently and take ownership of critical design aspects.

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NXP is committed to equal pay for equal work and work of equal value and applies fair, consistent and transparent remuneration practices.

More information about NXP in Italy...

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